(1) Field of the invention
This invention relates to a phase correction circuit of a sampling clock when a video signal from a video signal generation apparatus such as a graphic display is sampled by an output device such as a hard copy device.
(2) Background of the Invention
Output devices for conventional video signal generation apparatuses deal only with low frequency and strict phase correction including a temperature compensation employing a samping clock pulse phase has not been seen as necessary. In addition, re-adjustment has not been necessary, either, once the phase relation between the video signal and the sampling clock pulse has been made.
In graphic display devices used in recent CAD1CAM applications, a video frequency exceeding 100 MHz is used and in such an application, it is necessary to reproduce a picture with a high level of fidelity. In such a frequency range, however, a delay change quantity of circuit elements due to a temperature change exerts significant influences, and it is difficult even by use of a sampling clock pulse generation circuit relying upon a high precision PLL circuit to keep a phase drift below several nano seconds. For this reason, phase correction means must be used for video signals above 100 MHz.